home *** CD-ROM | disk | FTP | other *** search
/ Amiga Magazin: Amiga-CD 1997 September & October / Amiga-CD 1997 #9-10.iso / aminet / gameboyemulator / z80.c < prev    next >
C/C++ Source or Header  |  1995-10-29  |  15KB  |  409 lines
  1. /** VGB: portable GameBoy emulator ***************************/
  2. /**                                                         **/
  3. /**                           Z80.c                         **/
  4. /**                                                         **/
  5. /** This file contains implementation for the GameBoy CPU.  **/
  6. /** See Z80.h for the relevant definitions. Please, note    **/
  7. /** that this code can not be used to emulate a generic Z80 **/ 
  8. /** because the GameBoy version of it differs from Z80 in   **/
  9. /** many ways.                                              **/
  10. /**                                                         **/
  11. /** Copyright (C) Marat Fayzullin 1994,1995                 **/
  12. /**     You are not allowed to distribute this software     **/
  13. /**     commercially. Please, notify me, if you make any    **/   
  14. /**     changes to this file.                               **/
  15. /*************************************************************/
  16.  
  17. #include <stdio.h>
  18.  
  19. #include "GB.h"
  20.  
  21.  
  22. /*** Registers ***********************************************/
  23. /*** Z80 registers, RAM address, and running flag.         ***/
  24. /*************************************************************/
  25. static reg R;
  26. static byte *Addr;
  27. byte CPURunning;
  28.  
  29.  
  30. /*** Interrupts **********************************************/
  31. /*** Interrupt-related variables.                          ***/
  32. /*************************************************************/
  33. #ifdef INTERRUPTS
  34. word IPeriod = 10000; /* Number of cmds between int. intrpts */
  35. byte IntSync = 1;     /* 1 to generate internal interrupts   */
  36. byte IFlag = 0;       /* If IFlag==1, gen. int. and set to 0 */
  37. static word Cnt;      /* Variable used to count CPU cycles   */
  38. #endif
  39.  
  40.  
  41. /*** Trace and Trap ******************************************/
  42. /*** Switches to turn tracing on and off in DEBUG mode.    ***/
  43. /*************************************************************/
  44. #ifdef DEBUG
  45. byte Trace=0;       /* Tracing is on if Trace==1  */
  46. word Trap=0xFFFF;   /* When PC==Trap, set Trace=1 */
  47. word OldTrap = 0xFFFF;
  48. #endif
  49.  
  50.  
  51. /*** TrapBadOps **********************************************/
  52. /*** When 1, print warnings of illegal Z80 instructions.   ***/
  53. /*************************************************************/
  54. byte TrapBadOps=0;
  55.  
  56.  
  57. #define S(Fl)        R.AF.B.l|=Fl
  58. #define R(Fl)        R.AF.B.l&=~(Fl)
  59. #define FLAGS(Rg,Fl) R.AF.B.l=Fl|(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  60.  
  61. #define M_RLC(Rg)      \
  62.   R.AF.B.l=Rg&0x80? C_FLAG:0;Rg=(Rg<<1)|R.AF.B.l; \
  63.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  64. #define M_RRC(Rg)      \
  65.   R.AF.B.l=Rg&0x01;Rg=(Rg>>1)|(R.AF.B.l? 0x80:0); \
  66.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  67. #define M_RL(Rg)       \
  68.   if(Rg&0x80)          \
  69.   {                    \
  70.     Rg=(Rg<<1)|(R.AF.B.l&C_FLAG);               \
  71.     R.AF.B.l=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)|C_FLAG; \
  72.   }                    \
  73.   else                 \
  74.   {                    \
  75.     Rg=(Rg<<1)|(R.AF.B.l&C_FLAG);               \
  76.     R.AF.B.l=(Rg? 0:Z_FLAG)|(Rg&S_FLAG);        \
  77.   }
  78. #define M_RR(Rg)       \
  79.   if(Rg&0x01)          \
  80.   {                    \
  81.     Rg=(Rg>>1)|(R.AF.B.l&C_FLAG? 0x80:0);       \
  82.     R.AF.B.l=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)|C_FLAG; \
  83.   }                    \
  84.   else                 \
  85.   {                    \
  86.     Rg=(Rg>>1)|(R.AF.B.l&C_FLAG? 0x80:0);       \
  87.     R.AF.B.l=(Rg? 0:Z_FLAG)|(Rg&S_FLAG);        \
  88.   }
  89.   
  90. #define M_SLA(Rg)      \
  91.   R.AF.B.l=Rg&0x80? C_FLAG:0;Rg<<=1;              \
  92.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  93. #define M_SRA(Rg)      \
  94.   R.AF.B.l=Rg&C_FLAG;Rg=(Rg>>1)|(Rg&0x80);        \
  95.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  96.  
  97. #define M_SLL(Rg)      \
  98.   R.AF.B.l=Rg&0x80? C_FLAG:0;Rg=(Rg<<1)|0x01;     \
  99.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  100. #define M_SRL(Rg)      \
  101.   R.AF.B.l=Rg&0x01;Rg>>=1;                        \
  102.   R.AF.B.l|=(Rg? 0:Z_FLAG)|(Rg&S_FLAG)
  103.  
  104. #define M_BIT(Bit,Rg)  \
  105.   R.AF.B.l=(R.AF.B.l&~(N_FLAG|Z_FLAG))|H_FLAG|(Rg&(1<<Bit)? 0:Z_FLAG)
  106.  
  107. #define M_SET(Bit,Rg) Rg|=1<<Bit
  108. #define M_RES(Bit,Rg) Rg&=~(1<<Bit)
  109.  
  110. #define M_POP(Rg)      \
  111.   R.Rg.B.l=*(Addr+(R.SP.W++));R.Rg.B.h=*(Addr+(R.SP.W++));
  112. #define M_PUSH(Rg)     \
  113.   R.SP.W--;M_WRMEM(R.SP.W,R.Rg.B.h); \
  114.   R.SP.W--;M_WRMEM(R.SP.W,R.Rg.B.l)
  115.  
  116. #define M_CALL         \
  117.   J.B.l=*(Addr+(R.PC.W++));          \
  118.   J.B.h=*(Addr+(R.PC.W++));          \
  119.   R.SP.W--;M_WRMEM(R.SP.W,R.PC.B.h); \
  120.   R.SP.W--;M_WRMEM(R.SP.W,R.PC.B.l); \
  121.   R.PC.W=J.W
  122.  
  123. #define M_JP   J.B.l=*(Addr+(R.PC.W++));J.B.h=*(Addr+R.PC.W);R.PC.W=J.W
  124. #define M_JR   R.PC.W+=*(offset *)(Addr+R.PC.W)+1
  125. #define M_RET  R.PC.B.l=*(Addr+(R.SP.W++));R.PC.B.h=*(Addr+(R.SP.W++))
  126.  
  127. #define M_RST(Ad)      \
  128.   R.SP.W--;M_WRMEM(R.SP.W,R.PC.B.h); \
  129.   R.SP.W--;M_WRMEM(R.SP.W,R.PC.B.l); \
  130.   R.PC.W=Ad
  131.  
  132. #define M_LDWORD(Rg)   \
  133.   R.Rg.B.l=*(Addr+(R.PC.W++));R.Rg.B.h=*(Addr+(R.PC.W++))
  134.  
  135. #define M_ADD(Rg)      \
  136.   J.W=R.AF.B.h+Rg;     \
  137.   R.AF.B.l=            \
  138.     J.B.h|(J.B.l? 0:Z_FLAG)|(J.B.l&S_FLAG)|     \
  139.     ((R.AF.B.h^Rg^J.B.l)&H_FLAG);               \
  140.   R.AF.B.h=J.B.l       
  141.  
  142. #define M_SUB(Rg)      \
  143.   J.W=R.AF.B.h-Rg;     \
  144.   R.AF.B.l=            \
  145.     N_FLAG|-J.B.h|(J.B.l? 0:Z_FLAG)|(J.B.l&S_FLAG)|  \
  146.     ((R.AF.B.h^Rg^J.B.l)&H_FLAG);                    \
  147.   R.AF.B.h=J.B.l
  148.  
  149. #define M_ADC(Rg)      \
  150.   J.W=R.AF.B.h+Rg+(R.AF.B.l&C_FLAG);      \
  151.   R.AF.B.l=                               \
  152.     J.B.h|(J.B.l? 0:Z_FLAG)|(J.B.l&S_FLAG)|     \
  153.     ((R.AF.B.h^Rg^J.B.l)&H_FLAG);         \
  154.   R.AF.B.h=J.B.l
  155.  
  156. #define M_SBC(Rg)      \
  157.   J.W=R.AF.B.h-Rg-(R.AF.B.l&C_FLAG); \
  158.   R.AF.B.l=                          \
  159.     N_FLAG|-J.B.h|(J.B.l? 0:Z_FLAG)|(J.B.l&S_FLAG)|  \
  160.     ((R.AF.B.h^Rg^J.B.l)&H_FLAG);    \
  161.   R.AF.B.h=J.B.l
  162.  
  163. #define M_CP(Rg)       \
  164.   J.W=R.AF.B.h-Rg;     \
  165.   R.AF.B.l=            \
  166.     N_FLAG|-J.B.h|(J.B.l? 0:Z_FLAG)|(J.B.l&S_FLAG)|  \
  167.     ((R.AF.B.h^Rg^J.B.l)&H_FLAG)
  168.  
  169. #define M_AND(Rg)       \
  170.   R.AF.B.h&=Rg;         \
  171.   R.AF.B.l=H_FLAG|(R.AF.B.h&S_FLAG)|(R.AF.B.h? 0:Z_FLAG)
  172.  
  173. #define M_OR(Rg)        \
  174.   R.AF.B.h|=Rg;         \
  175.   R.AF.B.l=(R.AF.B.h&S_FLAG)|(R.AF.B.h? 0:Z_FLAG)
  176.  
  177. #define M_XOR(Rg)       \
  178.   R.AF.B.h^=Rg;         \
  179.   R.AF.B.l=(R.AF.B.h&S_FLAG)|(R.AF.B.h? 0:Z_FLAG)
  180.  
  181. #define M_INC(Rg)       \
  182.   Rg++;                 \
  183.   R.AF.B.l=             \
  184.     (R.AF.B.l&C_FLAG)|(Rg&S_FLAG)|     \
  185.     (Rg? 0:Z_FLAG)|(Rg&0x0F? 0:H_FLAG)
  186.  
  187. #define M_DEC(Rg)       \
  188.   Rg--;                 \
  189.   R.AF.B.l=             \
  190.     N_FLAG|(R.AF.B.l&C_FLAG)|(Rg&S_FLAG)|      \
  191.     (Rg? 0:Z_FLAG)|((Rg&0x0F)==0x0F? H_FLAG:0)
  192.  
  193. #define M_ADDW(Rg1,Rg2) \
  194.   R.AF.B.l=                                            \
  195.     (R.AF.B.l&~(N_FLAG|C_FLAG))|                       \
  196.     (((long)R.Rg1.W+(long)R.Rg2.W)&0x10000? C_FLAG:0); \
  197.   R.Rg1.W=(R.Rg1.W+R.Rg2.W)&0xFFFF;
  198.  
  199. #define M_ADCW(Rg)      \
  200.   I=R.AF.B.l&C_FLAG;J.W=(R.HL.W+R.Rg.W+I)&0xFFFF;            \
  201.   R.AF.B.l=                                                  \
  202.     (((long)R.HL.W+(long)R.Rg.W+(long)I)&0x10000? C_FLAG:0)| \
  203.     (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                          \
  204.   R.HL.W=J.W
  205.    
  206. #define M_SBCW(Rg)      \
  207.   I=R.AF.B.l&C_FLAG;J.W=(R.HL.W-R.Rg.W-I)&0xFFFF;            \
  208.   R.AF.B.l=                                                  \
  209.     N_FLAG|                                                  \
  210.     (((long)R.HL.W-(long)R.Rg.W-(long)I)&0x10000? C_FLAG:0)| \
  211.     (J.W? 0:Z_FLAG)|(J.B.h&S_FLAG);                          \
  212.   R.HL.W=J.W
  213.  
  214. #define M_IN(Rg)        \
  215.   Rg=DoIn(R.BC.B.l);    \
  216.   R.AF.B.l=(R.AF.B.l&C_FLAG)|(Rg&S_FLAG)|(Rg? 0:Z_FLAG)
  217.  
  218.  
  219. enum Codes
  220. {
  221.   NOP,LD_BC_WORD,LD_xBC_A,INC_BC,INC_B,DEC_B,LD_B_BYTE,RLCA,
  222.   EX_AF_AF,ADD_HL_BC,LD_A_xBC,DEC_BC,INC_C,DEC_C,LD_C_BYTE,RRCA,
  223.   DJNZ,LD_DE_WORD,LD_xDE_A,INC_DE,INC_D,DEC_D,LD_D_BYTE,RLA,
  224.   JR,ADD_HL_DE,LD_A_xDE,DEC_DE,INC_E,DEC_E,LD_E_BYTE,RRA,
  225.   JR_NZ,LD_HL_WORD,LD_xWORD_HL,INC_HL,INC_H,DEC_H,LD_H_BYTE,DAA,
  226.   JR_Z,ADD_HL_HL,LD_HL_xWORD,DEC_HL,INC_L,DEC_L,LD_L_BYTE,CPL,
  227.   JR_NC,LD_SP_WORD,LD_xWORD_A,INC_SP,INC_xHL,DEC_xHL,LD_xHL_BYTE,SCF,
  228.   JR_C,ADD_HL_SP,LD_A_xWORD,DEC_SP,INC_A,DEC_A,LD_A_BYTE,CCF,
  229.   LD_B_B,LD_B_C,LD_B_D,LD_B_E,LD_B_H,LD_B_L,LD_B_xHL,LD_B_A,
  230.   LD_C_B,LD_C_C,LD_C_D,LD_C_E,LD_C_H,LD_C_L,LD_C_xHL,LD_C_A,
  231.   LD_D_B,LD_D_C,LD_D_D,LD_D_E,LD_D_H,LD_D_L,LD_D_xHL,LD_D_A,
  232.   LD_E_B,LD_E_C,LD_E_D,LD_E_E,LD_E_H,LD_E_L,LD_E_xHL,LD_E_A,
  233.   LD_H_B,LD_H_C,LD_H_D,LD_H_E,LD_H_H,LD_H_L,LD_H_xHL,LD_H_A,
  234.   LD_L_B,LD_L_C,LD_L_D,LD_L_E,LD_L_H,LD_L_L,LD_L_xHL,LD_L_A,
  235.   LD_xHL_B,LD_xHL_C,LD_xHL_D,LD_xHL_E,LD_xHL_H,LD_xHL_L,HALT,LD_xHL_A,
  236.   LD_A_B,LD_A_C,LD_A_D,LD_A_E,LD_A_H,LD_A_L,LD_A_xHL,LD_A_A,
  237.   ADD_B,ADD_C,ADD_D,ADD_E,ADD_H,ADD_L,ADD_xHL,ADD_A,
  238.   ADC_B,ADC_C,ADC_D,ADC_E,ADC_H,ADC_L,ADC_xHL,ADC_A,
  239.   SUB_B,SUB_C,SUB_D,SUB_E,SUB_H,SUB_L,SUB_xHL,SUB_A,
  240.   SBC_B,SBC_C,SBC_D,SBC_E,SBC_H,SBC_L,SBC_xHL,SBC_A,
  241.   AND_B,AND_C,AND_D,AND_E,AND_H,AND_L,AND_xHL,AND_A,
  242.   XOR_B,XOR_C,XOR_D,XOR_E,XOR_H,XOR_L,XOR_xHL,XOR_A,
  243.   OR_B,OR_C,OR_D,OR_E,OR_H,OR_L,OR_xHL,OR_A,
  244.   CP_B,CP_C,CP_D,CP_E,CP_H,CP_L,CP_xHL,CP_A,
  245.   RET_NZ,POP_BC,JP_NZ,JP,CALL_NZ,PUSH_BC,ADD_BYTE,RST00,
  246.   RET_Z,RET,JP_Z,PFX_CB,CALL_Z,CALL,ADC_BYTE,RST08,
  247.   RET_NC,POP_DE,JP_NC,OUTA,CALL_NC,PUSH_DE,SUB_BYTE,RST10,
  248.   RET_C,EXX,JP_C,INA,CALL_C,PFX_DD,SBC_BYTE,RST18,
  249.   RET_PO,POP_HL,JP_PO,EX_HL_xSP,CALL_PO,PUSH_HL,AND_BYTE,RST20,
  250.   RET_PE,LD_PC_HL,JP_PE,EX_DE_HL,CALL_PE,PFX_ED,XOR_BYTE,RST28,
  251.   RET_P,POP_AF,JP_P,DI,CALL_P,PUSH_AF,OR_BYTE,RST30,
  252.   RET_M,LD_SP_HL,JP_M,EI,CALL_M,PFX_FD,CP_BYTE,RST38
  253. };
  254.  
  255. enum CodesCB
  256. {
  257.   RLC_B,RLC_C,RLC_D,RLC_E,RLC_H,RLC_L,RLC_xHL,RLC_A,
  258.   RRC_B,RRC_C,RRC_D,RRC_E,RRC_H,RRC_L,RRC_xHL,RRC_A,
  259.   RL_B,RL_C,RL_D,RL_E,RL_H,RL_L,RL_xHL,RL_A,
  260.   RR_B,RR_C,RR_D,RR_E,RR_H,RR_L,RR_xHL,RR_A,
  261.   SLA_B,SLA_C,SLA_D,SLA_E,SLA_H,SLA_L,SLA_xHL,SLA_A,
  262.   SRA_B,SRA_C,SRA_D,SRA_E,SRA_H,SRA_L,SRA_xHL,SRA_A,
  263.   SLL_B,SLL_C,SLL_D,SLL_E,SLL_H,SLL_L,SLL_xHL,SLL_A,
  264.   SRL_B,SRL_C,SRL_D,SRL_E,SRL_H,SRL_L,SRL_xHL,SRL_A,
  265.   BIT0_B,BIT0_C,BIT0_D,BIT0_E,BIT0_H,BIT0_L,BIT0_xHL,BIT0_A,
  266.   BIT1_B,BIT1_C,BIT1_D,BIT1_E,BIT1_H,BIT1_L,BIT1_xHL,BIT1_A,
  267.   BIT2_B,BIT2_C,BIT2_D,BIT2_E,BIT2_H,BIT2_L,BIT2_xHL,BIT2_A,
  268.   BIT3_B,BIT3_C,BIT3_D,BIT3_E,BIT3_H,BIT3_L,BIT3_xHL,BIT3_A,
  269.   BIT4_B,BIT4_C,BIT4_D,BIT4_E,BIT4_H,BIT4_L,BIT4_xHL,BIT4_A,
  270.   BIT5_B,BIT5_C,BIT5_D,BIT5_E,BIT5_H,BIT5_L,BIT5_xHL,BIT5_A,
  271.   BIT6_B,BIT6_C,BIT6_D,BIT6_E,BIT6_H,BIT6_L,BIT6_xHL,BIT6_A,
  272.   BIT7_B,BIT7_C,BIT7_D,BIT7_E,BIT7_H,BIT7_L,BIT7_xHL,BIT7_A,
  273.   RES0_B,RES0_C,RES0_D,RES0_E,RES0_H,RES0_L,RES0_xHL,RES0_A,
  274.   RES1_B,RES1_C,RES1_D,RES1_E,RES1_H,RES1_L,RES1_xHL,RES1_A,
  275.   RES2_B,RES2_C,RES2_D,RES2_E,RES2_H,RES2_L,RES2_xHL,RES2_A,
  276.   RES3_B,RES3_C,RES3_D,RES3_E,RES3_H,RES3_L,RES3_xHL,RES3_A,
  277.   RES4_B,RES4_C,RES4_D,RES4_E,RES4_H,RES4_L,RES4_xHL,RES4_A,
  278.   RES5_B,RES5_C,RES5_D,RES5_E,RES5_H,RES5_L,RES5_xHL,RES5_A,
  279.   RES6_B,RES6_C,RES6_D,RES6_E,RES6_H,RES6_L,RES6_xHL,RES6_A,
  280.   RES7_B,RES7_C,RES7_D,RES7_E,RES7_H,RES7_L,RES7_xHL,RES7_A,  
  281.   SET0_B,SET0_C,SET0_D,SET0_E,SET0_H,SET0_L,SET0_xHL,SET0_A,
  282.   SET1_B,SET1_C,SET1_D,SET1_E,SET1_H,SET1_L,SET1_xHL,SET1_A,
  283.   SET2_B,SET2_C,SET2_D,SET2_E,SET2_H,SET2_L,SET2_xHL,SET2_A,
  284.   SET3_B,SET3_C,SET3_D,SET3_E,SET3_H,SET3_L,SET3_xHL,SET3_A,
  285.   SET4_B,SET4_C,SET4_D,SET4_E,SET4_H,SET4_L,SET4_xHL,SET4_A,
  286.   SET5_B,SET5_C,SET5_D,SET5_E,SET5_H,SET5_L,SET5_xHL,SET5_A,
  287.   SET6_B,SET6_C,SET6_D,SET6_E,SET6_H,SET6_L,SET6_xHL,SET6_A,
  288.   SET7_B,SET7_C,SET7_D,SET7_E,SET7_H,SET7_L,SET7_xHL,SET7_A
  289. };
  290.   
  291. enum CodesED
  292. {
  293.   FUCK00,FUCK01,FUCK02,FUCK03,FUCK04,FUCK05,FUCK06,FUCK07,
  294.   FUCK08,FUCK09,FUCK0A,FUCK0B,FUCK0C,FUCK0D,FUCK0E,FUCK0F,
  295.   FUCK10,FUCK11,FUCK12,FUCK13,FUCK14,FUCK15,FUCK16,FUCK17,
  296.   FUCK18,FUCK19,FUCK1A,FUCK1B,FUCK1C,FUCK1D,FUCK1E,FUCK1F,
  297.   FUCK20,FUCK21,FUCK22,FUCK23,FUCK24,FUCK25,FUCK26,FUCK27,
  298.   FUCK28,FUCK29,FUCK2A,FUCK2B,FUCK2C,FUCK2D,FUCK2E,FUCK2F,
  299.   FUCK30,FUCK31,FUCK32,FUCK33,FUCK34,FUCK35,FUCK36,FUCK37,
  300.   FUCK38,FUCK39,FUCK3A,FUCK3B,FUCK3C,FUCK3D,FUCK3E,FUCK3F,
  301.   IN_B_xC,OUT_xC_B,SBC_HL_BC,LD_xWORDe_BC,NEG,RETN,IM_0,LD_I_A,
  302.   IN_C_xC,OUT_xC_C,ADC_HL_BC,LD_BC_xWORDe,FUCK4C,RETI,FUCK,LD_R_A,
  303.   IN_D_xC,OUT_xC_D,SBC_HL_DE,LD_xWORDe_DE,FUCK54,FUCK55,IM_1,LD_A_I,
  304.   IN_E_xC,OUT_xC_E,ADC_HL_DE,LD_DE_xWORDe,FUCK5C,FUCK5D,IM_2,LD_A_R,
  305.   IN_H_xC,OUT_xC_H,SBC_HL_HL,LD_xWORDe_HL,FUCK64,FUCK65,FUCK66,RRD,
  306.   IN_L_xC,OUT_xC_L,ADC_HL_HL,LD_HL_xWORDe,FUCK6C,FUCK6D,FUCK6E,RLD,
  307.   IN_F_xC,FUCK71,SBC_HL_SP,LD_xWORDe_SP,FUCK74,FUCK75,FUCK76,FUCK77,
  308.   IN_A_xC,OUT_xC_A,ADC_HL_SP,LD_SP_xWORDe,FUCK7C,FUCK7D,FUCK7E,FUCK7F,
  309.   FUCK80,FUCK81,FUCK82,FUCK83,FUCK84,FUCK85,FUCK86,FUCK87,
  310.   FUCK88,FUCK89,FUCK8A,FUCK8B,FUCK8C,FUCK8D,FUCK8E,FUCK8F,
  311.   FUCK90,FUCK91,FUCK92,FUCK93,FUCK94,FUCK95,FUCK96,FUCK97,
  312.   FUCK98,FUCK99,FUCK9A,FUCK9B,FUCK9C,FUCK9D,FUCK9E,FUCK9F,
  313.   LDI,CPI,INI,OUTI,FUCKA4,FUCKA5,FUCKA6,FUCKA7,
  314.   LDD,CPD,IND,OUTD,FUCKAC,FUCKAD,FUCKAE,FUCKAF,
  315.   LDIR,CPIR,INIR,OTIR,FUCKB4,FUCKB5,FUCKB6,FUCKB7,
  316.   LDDR,CPDR,INDR,OTDR,FUCKBC,FUCKBD,FUCKBE,FUCKBF,
  317.   FUCKC0,FUCKC1,FUCKC2,FUCKC3,FUCKC4,FUCKC5,FUCKC6,FUCKC7,
  318.   FUCKC8,FUCKC9,FUCKCA,FUCKCB,FUCKCC,FUCKCD,FUCKCE,FUCKCF,
  319.   FUCKD0,FUCKD1,FUCKD2,FUCKD3,FUCKD4,FUCKD5,FUCKD6,FUCKD7,
  320.   FUCKD8,FUCKD9,FUCKDA,FUCKDB,FUCKDC,FUCKDD,FUCKDE,FUCKDF,
  321.   FUCKE0,FUCKE1,FUCKE2,FUCKE3,FUCKE4,FUCKE5,FUCKE6,FUCKE7,
  322.   FUCKE8,FUCKE9,FUCKEA,FUCKEB,FUCKEC,FUCKED,FUCKEE,FUCKEF,
  323.   FUCKF0,FUCKF1,FUCKF2,FUCKF3,FUCKF4,FUCKF5,FUCKF6,FUCKF7,
  324.   FUCKF8,FUCKF9,FUCKFA,FUCKFB,FUCKFC,FUCKFD,FUCKFE,FUCKFF
  325. };
  326.  
  327.  
  328. #ifdef LAME
  329. #include "Lame.h"
  330. #else
  331. word Z80(register byte *Addr,reg Regs)
  332. {
  333.   register byte I;
  334.   register pair J;
  335.   
  336.   R=Regs;
  337.  
  338. #ifdef INTERRUPTS
  339.   Cnt=IPeriod;
  340. #endif
  341.  
  342.   for(CPURunning=1;CPURunning;)
  343.   {
  344.     LCDSTAT=(LCDSTAT&0xFC)|((Cnt>>5)&0x03);
  345.  
  346.     switch(*(Addr+(R.PC.W++)))
  347.     {
  348. #include "Codes.h"
  349.  
  350.       case PFX_CB:
  351.         switch(*(Addr+(R.PC.W++)))
  352.         {
  353. #include "CodesCB.h"
  354.           default:
  355.             if(TrapBadOps)
  356.               printf("Unrecognized CB instruction at PC=%hX\n",R.PC.W-2);
  357.         }
  358.         break;
  359.  
  360.       case PFX_ED:
  361.         switch(*(Addr+(R.PC.W++)))
  362.         {
  363. #include "CodesED.h"
  364.           default:
  365.             if(TrapBadOps)
  366.               printf("Unrecognized ED instruction at PC=%hX\n",R.PC.W-2);
  367.         }
  368.         break;
  369.  
  370.       case 0x10:
  371.       case HALT:
  372. #ifdef INTERRUPTS
  373.         if(Cnt) R.PC.W--; else R.IFF|=0x01;
  374. #else
  375.         printf("CPU HALTed and stuck at PC=%hX\n",--R.PC.W); 
  376.         return(R.PC.W);
  377. #endif
  378.         break;
  379.  
  380.       default:
  381.         if(TrapBadOps)
  382.           printf("Unrecognized instruction at PC=%hX\n",R.PC.W-1);
  383.     }
  384.  
  385. #ifdef INTERRUPTS
  386.     /*** Here we generate NMI if Cnt reaches 0: ***/ 
  387.     if(!Cnt--) 
  388.     { 
  389.       Cnt=IPeriod;
  390.       if(IntSync) IFlag=1;
  391.     }
  392.     if(IFlag)
  393.     {
  394.       IFlag=0;J.W=Interrupt();
  395.       if((J.W!=0xFFFF)&&(R.IFF&0x01))
  396.       { M_PUSH(PC);R.PC.W=R.IFF&0x04? ((word)R.I<<8)+0xFF:J.W; }
  397.     }
  398. #endif
  399.  
  400. #ifdef DEBUG
  401.     if(R.PC.W==Trap) Trace=1;  /*** Turn tracing on if trapped ***/
  402.     if(Trace) Z80_Debug(Addr,R);   /*** Call single-step debugger  ***/
  403. #endif
  404.  
  405.   }
  406.   return(R.PC.W);
  407. }
  408. #endif
  409.